Your Role: 
<ul>
<li>Own SoC memory controller &amp; PHY micro architecture including integration into SoC</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Analyze complex data flows at the subsystem and full chip level.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Have good knowledge on The JEDEC memory specifications for semiconductor memory circuits and similar storage devices.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Strong experience with using 3rd party Memory controllers and PHYs for (LP)DDR4, 5, 6 and HBM 2,3,4.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Perform high-level performance modeling/simulation and analysis of memory controller features, applications, benchmarks, and complex uses cases</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Define performance enhancement techniques such as end to end hashing for the performance</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Work with the 3rd party IP vendors to make sure SoC power and performance targets per use cases are fully covered with their IP offering. </li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Interact with the design partner teams to define IP integration, SoC flows to make sure SoC level targets are met.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Work with design partner and IP teams to review Lint, CDC, SDC, Verification strategy at SoC level.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Work with IP vendor and design partners to make sure coherency through the fabric, end to end latency, data flow, performance requirements are met.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Track changes, progress on additional features required from IP vendor specific for Aptiv SoC.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Coach and mentor others in your areas of expertise </li>
</ul>
Your Background: 
<ul>
<li style="margin-left:1.6rem;">Bachelor’s degree in electrical engineering, computer engineering, or equivalent.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">12 + years of experience in ARM CPU based full chip SoC development.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Experience with SoC subsystem and full chip development for a complex silicon project from concept to launch.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Strong experience with using 3rd party Memory controllers and PHYs for (LP)DDR4, 5, 6 and HBM2,3,4.</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">High proficiency in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation, especially around fabric, system cache and memory controller</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Ability to leverage existing simulation capabilities (GEM5, FastSIM, Platform Architect) or create new simulation capabilities when necessary</li>
</ul>

<ul>
<li style="margin-left:1.6rem;">Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB), JEDEC standards</li>
</ul>

Semiconductor Design Engineer in Dharuhera (UID-7638)

Job Description

Job Details

Skills Required for Semiconductor Design Engineer

Job Description for Semiconductor Design Engineer

Explore More Opportunities